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1 copyright ? c i r r us logic, i n c. 1999 (all r i ght s reserv ed) cirrus log ic, i n c. p.o . box 178 47, aus t in , te xa s 7 876 0 (5 12) 445 72 22 fax: ( 512 ) 44 5 75 81 h ttp :/ /www.c r ysta l . c o m prelimin ary produ ct inform ation this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. cs5181 ds mo dul at or & 40 0 khz t o 62 5 khz 1 6 - b i t adc features l 16-bit delta-sigma a/d converter l fully differential input with 4.0 v pp range l dynamic range: 93 db l spurious free dynamic range: 90 dbc l harmonic distortion: 89 db l up to 625 khz output word rate l no missing codes l non-aliasing low-pass digital filter l high speed 3-wire serial interface l supply requirements: - va+ = 5 v, vd+ = 3.3 v: 570 mw l modulator output mode l power-down mode description cs5181 is a fully calibrated high-speed ds analog-to- digital converter, capable of 625 ksamples/second out- put word rate (owr). the owr scales with the master clock. it consists of a 5th order ds modulator, decimation filter, and serial interface. the chip can use the 2.375 v on-chip voltage reference, or an external 2.5 v refer- ence. the input voltage range is 1.6 vrefin v pp fully differential. multiple cs5181s can be fully synchronized in multi-channel applications with a sync signal. the part has a power-down mode to minimize power consump- tion at times of system inactivity. the high speed digital i/o lines have complementary signals to help reduce ra- diated noise from traces on the pc board layout. the cs5181 can also be operated in modulator-only mode which provides the delta-sigma modulator bitstream as the output. ordering information CS5181-BL -40 c to +85 c 28-pin plcc i ain+ ain- vref+ vrefin vrefout vrefcap pwdn sync reset mode va+ agnd vd+ dgnd mclk mclk mflag sdo sdo sclk sclk fso decimator clock x1.6 reference timing and control serial interface ds modulator vref- mode selector apr 99 ds250pp1
cs5181 2 ds250pp1 table of contents characteristics/specifications ............................................................ 4 analog characteristics................................................................... 4 dynamic characteristics ................................................................. 5 digital characteristics.................................................................... 5 switching characteristics ............................................................. 6 recommended operating conditions .......................................... 7 absolute maximum ratings .............................................................. 7 general description .................................................................................. 8 theory of operation .................................................................................. 8 converter initialization: calibration and synchronization .......................... 8 clock generator .......................................................................................... 9 voltage reference ...................................................................................... 9 analog input ............................................................................................. 10 output coding .......................................................................................... 10 modulator-only mode ............................................................................... 10 instability indicator .................................................................................... 12 digital filter characteristics ...................................................................... 12 serial interface .......................................................................................... 12 power supplies / board layout ................................................................ 12 power-down mode .................................................................................... 14 pin descriptions ......................................................................................... 15 parameter definitions ............................................................................. 18 appendix a: circuit applications ......................................................... 20 package outline dimensions ................................................................. 23 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs5181 ds250pp1 3 table of figures 1. serial port timing (not to scale) .............................................................................. 6 2. reset and sync logic and timing. ....................................................................... 8 3. cs5181 connection diagram for using the internal voltage reference. .................... 9 4. cs5181 connection diagram for using an external voltage reference. .................. 10 5. modulator only mode data rtz format. .............................................................. 11 6. circuit to reconstruct return-to-zero (rtz) data from sdo/sdo into original modulator bitstream.... 11 7. magnitude versus frequency spectrum of modulator bitstream (mclk = 40.0 mhz). .............................................................................................. 11 8. expanded view of the magnitude versus frequency spectrum of modulator bitstream (mclk = 40 mhz). ................................................................................. 11 9. cs5181 digital filter magnitude response (mclk = 40 mhz) ............................. 12 10. cs5181 digital filter phase response (mclk = 40 mhz) ................................... 12 11. cs5181 system connection diagram ................................................................... 13 12. single amplifier driving only ain+, with ain- held at a steady dc value ................ 20 13. performance of amplifier of figure 11 overdriving ain+ input to the cs5181 at 3.8 vpp ............................................................................................... 20 14. performance of amplifier of figure 11 with ain+ driven at 2.0 vpp ...................... 20 15. four amplifier balanced driver. .............................................................................. 21 16. performance of amplifier in figure 14 ................................................................... 21 17. performance of amplifier in figure 14 ................................................................... 22 18. cs5181 differential non-linearity plot. (data taken with repeating ramp) ............ 22 19. histogram of dnl from figure 17 ......................................................................... 22 20. cs5181 noise histogram, 32768 samples. ......................................................... 22
cs5181 4 ds250pp1 characteristics/specifications analog characteristics (t a = -40 to 85 c; va+ = 5 v 5%, vd+ = 3.3 v 0.3v; agnd = dgnd = 0 v; mclk = 40.0 mhz; vrefin = vrefout; mode = vd+; analog source impedance = 301 ohms with 2200 pf to agnd; full-scale input sinewave at 22 khz; unless otherwise noted.) notes: 1. dynamic range is tested with a 22 khz input signal 60 db below full scale. 2. specification guaranteed by design, characterization, and/or test. 3. full scale fully-differential input span is nominally 1.6 x the vrefin voltage. the peak negative excursion of the signals at ain+ or ain- should not go below agnd for proper operation. 4. vrefin current is less than 1 a under normal operation, but can be as high as 320 a during calibration. 5. drift of the on-chip reference alone is typically about 30 ppm/c. if using an external reference, total full scale drift will be that of the external reference plus an additional 20 ppm/c, which is the typical drift of the x1.6 buffer. 6. applies after self-calibration at final operating ambient temperature. parameter symbol min typ max unit dynamic performance dynamic range (note 1) dr 89 93 - db total harmonic distortion @ 22 khz (note 1) thd 84 89 - db signal to (noise + distortion) sinad 82 87 - db spurious free dynamic range sfdr 84 90 - dbc static performance integral nonlinearity (note 2) inl - 2 - lsb differential non-linearity (note 2) dnl - - 0.5 lsb full scale error (note 6) - 8 - lsb full scale drift with internal reference (notes 2 and 5) - 50 - ppm/c offset error (note 6) - 8 - lsb offset drift (note 2) - 6.0 - v/c analog input differential input voltage range (note 3) - 1.6 x vrefin -v pp common mode range cmr 1 - vrefin + 0.25 v input capacitance - 4.0 - pf differential input impedance (capacitive) - 300 - k w common mode rejection ratio (note 2) cmrr 50 - - db common mode input current - 160 320 a reference input vrefin 2.25 2.375 2.6 v vrefin current (note 4) - 1 320 a reference output vrefout voltage 2.25 2.375 2.5 v vrefout output current - - 500 a vrefout impedance - 0.1 - w
cs5181 ds250pp1 5 analog characteristics (continued) notes: 7. all outputs unloaded. all inputs except mclk held static at vd+ or dgnd. 8. power consumption when pwdn = 0 applies only for no master clock applied (mclk held high or low). 9. measured with a 100 mv pp sine wave on the va+ supplies at a frequency of 100 hz. dynamic characteristics digital characteristics (t a = -40 to 85 c; vd = 3.3v 0.3v; agnd = dgnd = 0 v) specifications are subject to change without notice. parameter symbol min typ max unit power supplies power supply current (mode = 1, pwdn = 1) (note 7) va1+, va2+ = 5 v vd1+, vd2+ = 3.3 v - - 53 92.4 65 100 ma ma power supply current (mode = 1, pwdn = 0) (notes 7, 8) va1+, va2+ = 5 v vd1+, vd2+ = 3.3 v - - 3.7 0.062 6 0.2 ma ma power supply current (mode = 0, pwdn = 1) (note 7) va1+, va2+ = 5 v vd1+, vd2+ = 3.3 v - - 53 18.9 65 22 ma ma power supply current (mode = 0, pwdn = 0) (notes 7, 8) va1+, va2+ = 5 v vd1+, vd2+ = 3.3 v - - 3.7 0.062 6 0.2 ma ma power supply rejection (note 9) psrr - 55 - db parameter symbol min typ max unit modulator sampling frequency - mclk - hz output word rate - mclk/64 - hz filter characteristics (note 2) -3 db corner - mclk/142.3804 - hz passband ripple - - 0.05 db stopband frequency - mclk/128 - hz stopband rejection 90 - - db group delay - 2370/mclk - s parameter symbol min typ max unit high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (i o = -100 a) v oh 2.7 - - v low-level output voltage (i o = 100 a) v ol --0.3v input leakage current i in -110a input capacitance cin - 6 - pf
cs5181 6 ds250pp1 switching characteristics (t a = -40 to 85 c; va+ = 5 v 5%, vd+ = 3.3 v 0.3 v; agnd = dgnd = 0 v; mode = vd+) notes: 10. rise and fall times are specified at 10% to 90% points on waveform. 11. reset , sync, and pwdn have schmitt-trigger inputs. 12. specifications applicable to complementary signals sclk and sdo . parameter symbol min typ max unit master clock frequency (note 2) mclk 0.512 25 to 40 41 mhz master clock duty cycle 45 - 55 % rise times (notes 2, 10, and 11) any digital input, except mclk mclk any digital output t rise - - - - - 20 100 .2/mclk - ns s ns fall times (notes 2, 10, and 11) any digital input, except mclk mclk any digital output t fall - - - - - 20 100 .2/mclk - ns s ns calibration/sync reset rising to mclk rising -3 -ns reset rising recognized, to fso falling - 988205/mclk - s sync rising to mclk rising - 3 - ns sync rising recognized to fso falling - 5161/mclk - s pwdn rising recognized to fso falling - 5168/mclk - s sync high time 1/mclk - - s reset low time 1/mclk - - s serial port timing (note 12) sclk frequency - mclk/3 - hz sclk high time t 1 -1/mclk -s sclk low time t 2 -2/mclk -s fso falling to sclk rising t 3 -2/mclk+2e-9 - s sclk falling to new data bit t 4 -1.5 -ns sclk rising to fso rising t 5 -1/mclk-2e-9 - s fso sclk sdata xx msb msb-1 lsb-1 lsb xx t 1 t 2 t 3 t 4 t 5 figure 1. serial port timing (not to scale)
cs5181 ds250pp1 7 recommended operating conditions (agnd = dgnd = 0 v) absolute maximum ratings warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. specifications are subject to change without notice. parameter symbol min typ max unit dc power supplies digital analog vd+ va+ 3.0 4.75 3.3 5 3.6 5.25 v v analog reference voltage vrefin 2.25 2.5 2.6 v agnd to dgnd differential -100 0 100 mv operating junction temperature t j --120 c parameter symbol min max unit dc power supplies ground digital analog agnd/dgnd vd+ va+ -0.3 -0.3 -0.3 (vd+) + 0.3 6.0 6.0 v v v input current, any pin except supplies i in -10ma output current i out -25ma power dissipation (total) - 1000 mw analog input voltage v ina -0.3 (va+) + 0.3 v digital input voltage v ind -0.3 (vd+) + 0.3 v ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c
cs5181 8 ds250pp1 general description the cs5181 is a monolithic cmos 16-bit a/d converter designed to operate in continuous mode after being reset. the cs5181 can operate in modulator-only mode in which the bit stream from the modulator is the data output from the device. theory of operation the front page of this data sheet illustrates the block diagram of the cs5181. converter initialization: calibration and synchronization the cs5181 does not have an internal power-on re- set circuit. therefore when power is first applied to the device the reset pin should be held low until power is established. this resets the converters log- ic to a known state. when power is fully established the converter will perform a self-calibration, starting with the first mclk rising edge after reset goes high. the converter will use 988,205 mclk cycles to complete the calibration and to allow the digital filter to fully settle, after which, it will output fully- settled conversion words. the converter will then continue to output conversion words at an output word rate equal to mclk/64. figure 2 illustrates the reset and sync logic and timing for the con- verter. the cs5181 is designed to perform conversions continuously with an output rate that is equivalent to mclk/64. the conversions are performed and the serial port is updated independent of external controls. the converter is designed to measure dif- ferential bipolar input signals, and unipolar signals, with a common mode voltage of between 1.0 v and vref + 0.25 v. calibration is performed when the reset signal to the device is released. if reset is properly framed to mclk, the converter can be synchronized to a specific mclk cycle at the sys- tem level. the sync signal can also be used to synchronize multiple converters in a system. when sync is used, the converter does not perform calibration. the sync signal is recognized on the first rising edge of mclk after sync goes high. sync aligns the output conversion to occur every 64 mclk clock cycles after the sync signal is rec- ognized and the filter is settled. after the sync is initiated by going high, the converter will wait 5,161 mclk cycles for the digital filter to settle before putting out a fully-settled conversion word. to synchronize multiple converters in a system, the sync pulse should rise on a falling edge of the mclk signal. this ensures that the sync input to all cs5181s in the system will be recognized on the next rising edge of mclk. use of the sync input reset mclk sync cs5181 d clk q q reset mclk reset fso 988205 mclk cycles d clk qsync mclk sync fso 5161 mclk cycles figure 2. reset and sync logic and timing.
cs5181 ds250pp1 9 is not necessary to make the converter operate properly. if it is unused it should be tied to dgnd. conversion data is output from the sdo and sdo pins of the device. the data is output from the sdo pin msb first, in twos complement format. the converter furnishes a serial clock sclk and its complement sclk to latch the data bits; and a data frame signal, frame signal output (fso), which frames the output conversion word. the sclk output frequency is mclk/3. clock generator the cs5181 must be driven from a cmos-com- patible clock at its mclk pin. the mclk input is powered from the vd+ supply and its signal input should not exceed this supply. the required mclk is 64 owr (output word rate). to achieve an output word rate of 625 khz, the mclk frequency must be 64 625 khz, or 40 mhz. a second clock input pin, mclk , is not actually used inside the device but allows the user to run a fully differential clock to the converter to minimize radiated noise from the pc board layout. the cs5181 can be operated with mclk frequen- cies from 512 khz up to 40 mhz. the output word rate scales with the mclk rate with owr = mclk/64. voltage reference the cs5181 can be configured to operate from ei- ther its internal voltage reference, or from an exter- nal voltage reference. the on-chip voltage reference is nominally 2.375 v and is referenced to the agnd pins. this 2.375 v reference is output from the vrefout pin. it is then filtered and returned to the vrefin pin. the vrefin pin is connected to a buffer which has a typical gain of 1.6. this scales the on-chip reference of 2.375 v to 3.8 v. this value sets the peak-to-peak input voltage into the ain pins of the converter. fig- ure 3 illustrates the cs5181 connected to use the in- ternal voltage reference. note that a 1.0 f and 0.1 f capacitor are shown connected to the vrefcap pin to filter out noise. a larger capacitor can be used, but may require a longer reset period when first pow- ering up the part to allow for the reference to stabilize before the part self-calibrates. alternatively, the cs5181 can be configured to use an external voltage reference. figure 4 illustrates the cs5181 connected to use a 2.5 v external ref- erence. in this case, the maximum peak-to-peak signal input at the ain pins is 4.0 v. 10 f 0.1 f + vrefin vref+ vref- vrefout vrefcap x1.6 x1 modulator reference cs5181 10 f 0.1 f + 1 f 0.1 f + figure 3. cs5181 connection diagram for using the internal voltage reference.
cs5181 10 ds250pp1 analog input the analog signal to the converter is input into the ain+ and ain- pins. the input signal is fully dif- ferential with the maximum peak-to-peak ampli- tude of vrefin x 1.6 v. the signal needs to have a common mode voltage in a range from 1.0 v to vref + 0.25 v for minimum distortion. a resis- tor-capacitor filter should be included on the ain+ and ain- inputs of the converter. this should con- sist of a 20 w resistor and a 2200 pf capacitor on each input to ground as illustrated in the system connection diagram (figure 11). output coding table 1 illustrates the output coding for the con- verter when operating with the digital filter (mode = 1). the converter outputs its data from the serial port in twos complement format, msb first. the chip offers an mflag signal to indicate when the modulator has gone unstable. mflag is set when an overrange signal forces the modulator into an unstable condition. under this condition, output codes from the converter will be locked to either plus or minus full scale as is appropriate for the overrange condition. modulator-only mode the cs5181 can be operated in modulator-only mode by connecting the mode pin to a logic 0 (dgnd). in modulator-only mode the noise-shaped bit- stream from the fifth-order delta-sigma modulator is output from the sdo and sdo (inverse bit- stream) pins. 10 f 0.1 f + vrefin vref+ vref- vrefout vrefcap x1.6 x1 modulator reference cs5181 10 f 0.1 f + 1 f 0.1 f + 10 f 0.1 f + 2.5 v 10 f 0.1 f + vs figure 4. cs5181 connection diagram for using an external voltage reference. fully differential bipolar input voltage 1 twos complement >(v fs - 1.5 lsb) 7fff v fs - 1.5 lsb 7fff 7ffe -0.5 lsb 0000 ffff -v fs + 0.5 lsb 8001 8000 <(-v fs + 0.5 lsb) 8000 notes: 1. v fs = vrefin x 1.6 table 1. output coding.
cs5181 ds250pp1 11 the data from the modulator is output from sdo/sdo in rtz (return to zero) format. the circuit in figure 6 can be used to reconstruct the data so it can be captured with the rising or falling edge of mclk. table 2 illustrates the magnitude of the input signal into the chip versus the ones density out of the modulator. the table does not take into account the potential offset and gain errors of the modulator and their effect on the ones density. figure 7 and figure 8 illustrate magnitude versus frequency plots of the modulator bitstream when running at 40.0 mhz. fully differential bipolar input voltage 2 modulator ones density 3 v fs 75% 050% -v fs 25% notes: 2. v fs = vrefin x 1.6 3. ones density is approximate; it does not take offset and gain errors into consideration. table 2. modulator-only mode ones density. mclk modulator data sdo reconstructed data sdo figure 5. modulator only mode data rtz format. sdo reconstructed data sdo reconstructed data figure 6. circuit to reconstruct return-to-zero (rtz) data from sdo/sdo into original modulator bitstream. figure 7. magnitude versus frequency spectrum of modulator bitstream (mclk = 40.0 mhz). figure 8. expanded view of the magnitude versus fre- quency spectrum of modulator bitstream (mclk = 40 mhz).
cs5181 12 ds250pp1 instability indicator the mflag signal is functional in both modes of operation of the part and indicates when the modu- lator has been overdriven into an unstable condi- tion. in the modulator only mode (mode = 0), the mflag signal will remain set for 3 mclk cycles when the modulator goes unstable, before being re- turned to the reset state. while the input condition causing modulator instability persists, the mflag signal will continually get set for 3 mclk cycles and then get reset. when the decimation filter on the part is operation- al (mode = 1), the mflag signal is set when the modulator goes unstable. in this mode, however, the mflag signal stays set until 5,120 mclk cy- cles after the input condition causing modulator in- stablility is removed. this delay is provided to allow the digital filter time to settle, and the part will output fully settled conversion words after the mflag signal goes low. digital filter characteristics figure 9 illustrates the magnitude versus frequency plot of the converter when operating at a 625 khz output word rate. the filter is a non-aliasing 4265 tap filter with a -3 db corner at 0.4495 of the output word rate and an out-of-band attenuation of at least 90 db at frequencies above one half the output word rate. the passband ripple is less than 0.05 db up to the -3 db corner frequency. figure 10 illustrates the phase response of the dig- ital filter with the converter operating at 625 khz output word rate. the filter characteristics change proportional to changes in the mclk rate. the group delay of the digital filter is 2370 mclk cycles (59.3 s with mclk = 40 mhz), and the settling time is 4740 mclk cycles (118.5 s). serial interface the cs5181 has a serial interface through which conversion words are output in a synchronous self- clocking format. the serial port consists of the se- rial data output pin (sdo), and its complement (sdo ); serial clock (sclk), and its complement (sclk ); and the frame sync output (fso). fso falls at the beginning of an output word. data is output in twos complement format, msb first. fso stays low for 16 sclk cycles. sclk is out- put at a rate equal to mclk/3. power supplies / board layout the cs5181 requires an analog supply voltage of 5.0 volts and a digital supply voltage of 3.3 volts (nominal) for proper operation. figure 9. cs5181 digital filter magnitude response (mclk = 40 mhz) -250.00 -200.00 -150.00 -100.00 -50.00 0.00 50.00 100.00 150.00 200.00 250.00 0 50k 100k 150k 200k 250k 300k freq (hz) phase (deg.) figure 10. cs5181 digital filter phase response (mclk = 40 mhz)
cs5181 ds250pp1 13 figure 11 illustrates the system connection diagram for the chip. for best performance, each of the supply pins should be bypassed to the nearest ground pin on the chip. the bypass capacitors should be located as close to the chip as possible. if the chip is surface mounted the bypass capacitors should be on the same side of the circuit card as the chip. the cs5181 is a high speed component that re- quires adherence to standard high-frequency print- ed circuit board layout techniques to maintain optimum performance. these include the use of ground and power planes, using low noise power supplies in conjunction with proper supply decou- pling, minimizing circuit trace lengths, and physi- cal separation of digital and analog components and circuit traces. it is preferred that any clock oscillator circuitry be located on a ground plane separate from the digital plane in order to ensure that digital noise does not induce clock jitter. for additional insight, see the cdb5181 evaluation board for more details. also refer to application note an18 which covers layout and design rules for high resolution data converters. agnd1 +5 v + + + ~ 3.8 v fully differential cmv = 2.375 v pp +3.3 v va1+ va2+ agnd2 agnd3 vrefout vrefin vref- vref+ vrefcap ain+ ain- dgnd1 vd1+ vd2+ dgnd2 pwdn mode reset sync mflag mclk mclk fso sclk sdo sclk sdo control logic clock source data interface cs5181 1 28 8 7 18 4 5 3 2 6 26 27 22 21 12 11 25 24 23 10 9 20 19 17 14 13 16 15 the 3.8 v fully differential input span is set by the converter's internal voltage reference at 2.375 v. an input span of 4.0 v fully differential would result if an external voltage reference of 2.5 v is used. pp pp 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 10 f 1 f 2200 pf 2200 pf 20 w 20 w figure 11. cs5181 system connection diagram
cs5181 14 ds250pp1 power-down mode the cs5181 has a pwdn (power-down) function. when active low, power to most of the converters circuitry will be reduced. if mclk is to be stopped to save power, it should not be stopped until at least ten clock cycles after pwdn is taken low. the ten clock cycles are required to allow the part to turn off its internal circuitry. if the part does not get the full ten clock cycles, it will still go into a power down state, but the power dissipation could be more than is listed in the specifications for the full power down condition. when pwdn is active, the calibration information inside of the converter is maintained. when coming out of the power-down state, the converter is not recalibrated and will start-up similar to when sync is initiated.
cs5181 ds250pp1 15 pin descriptions analog ground agnd pos. reference vref+ va1+ positive analog supply neg. reference vref- ain- negative analog input reference output vrefout ain+ positive analog input pos. reference input vrefin pwdn power down mode reference bypass vrefcap mode modulator only mode analog ground agnd reset reset and calibration analog supply va2+ dgnd digital ground invalid conversion mflag vd1+ positive digital supply sync. filter sync mclk master clock digital ground dgnd mclk inverse master clock pos. digital supply vd2+ agnd analog ground inverse serial clock sclk fso frame sync output serial clock sclk sdo serial data out sdo inverse serial data out\ cs5181 1 2 3 4282726 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 18 agnd analog ground analog ground agnd va1+ positive analog supply pos. reference vref+ agnd analog ground neg. reference vref- ain- negative analog input reference output vrefout ain+ positive analog input analog ground agnd agnd analog ground analog ground agnd pwdn power down mode reference input vrefin mode modulator only mode reference bypass vrefcap reset reset and calibration analog ground agnd dgnd digital ground analog ground agnd dgnd digital ground analog supply va2+ vd1+ positive digital supply analog supply va2+ vd1+ positive digital supply invalid conversion mflag dgnd digital ground sync. filter sync mclk master clock digital ground dgnd mclk inverse master clock digital ground dgnd dgnd digital ground pos. digital supply vd2+ nc pos. digital supply vd2+ agnd analog ground digital ground dgnd nc inverse serial clock sclk fso frame sync output serial clock sclk sdo serial data out sdo inverse serial data out\ 1 2 3 4 5 6 7 8 9 10 11 12131415 16171819202122 33 32 31 30 29 28 27 26 25 24 23 4443424140393837363534 cs5181
cs5181 16 ds250pp1 supply inputs va1+, va2+ positive analog supply input for the positive analog supply is +5.0 v typical when agnd is 0 v. agnd analog ground analog ground for circuits supplied by va+. vd1+, vd2+ positive digital supply input for positive digital supply is +3.3 v typical when dgnd is 0 v. dgnd digital ground digital ground for circuits supplied by vd+. signal and reference related inputs ain+, ain- differential analog inputs fully differential signal inputs. vrefin voltage reference input vrefout or an external reference is connected to vrefin. analog input voltage (full scale fully differential peak-to-peak) into the converter is 1.6 times this value. vref+ positive voltage reference filter capacitor connection for the reference input buffer. the voltage on this pin equals vrefin x 1.6. vref- negative voltage reference vref- is connected to agnd. vrefout voltage reference output output pin for the 2.375 volt on-chip reference relative to agnd. vrefcap reference bypass filter capacitor connection for internal reference. serial interface i/o signals sclk, sclk serial interface clock serial clock output. a gated serial clock output from the converter at a rate equal to 1/3 the mclk clock rate. the sclk output is a complement of sclk and helps reduce radiated noise if the two lines are run adjacent on the pc board layout and drive a balanced load.
cs5181 ds250pp1 17 sdo, sdo serial data out serial data output. output pin for 16-bit serial data word. the sdo output is the complement of sdo and helps to reduce radiated noise if the two lines are run adjacent on the pc board layout. output data is output in twos complement format msb first. fso frame sync output frame sync output. the frame sync output turns low to indicate the beginning of an output word from the sdo pin. it returns high after the 16 data bits have been clocked out. control pins reset reset and calibration when the reset pin is pulled to a logic low the converter will perform a reset of its digital logic. when the level on this pin is brought back to a logic high the chip starts normal operation, following a two clock cycle delay period. when mode = 1, the chip goes through an internal gain and offset calibration routine following this reset sequence. pwdn power down mode a logic 0 on the pwdn pin will put the device into a power-down mode. mode modulator only mode mode is held at a logic high for normal operation. in normal operation the device utilizes the digital decimation filter and calibration ciruitry. mode = 0 puts the part in modulator only mode whereby most of the digital circuitry is powered-down and the modulator bit-stream is output from the sdo and sdo pins. sync synchronization of filter the sync input can be used to restart the digital filter of the converter at the beginning of its convolution cycle. the sync input is used to synchronize the filters of multiple converters in a system. when the sync signal goes high, the filter will be initialized and will begin its convolution cycle on the next rising edge of mclk. if not used, tie sync to dgnd. mflag invalid conversion flag mflag goes high if the modulator portion of the converter goes unstable. if mflag is high, the output data from the converter may be invalid. mclk, mclk master clock signal master clock input accepts a cmos level clock input to the converter with worst case duty cycle of 45-55% (typically 40 mhz). mclk is not actually used inside the device, but can be used for radiated noise cancellation if mclk and mclk are run adjacent to each other on the pc board.
cs5181 18 ds250pp1 parameter definitions differential non-linearity error - dnl the deviation of a codes width from ideal. units in lsbs. integral non-linearity error - inl the deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "zero-scale" is a point 1/2 lsb below the first code transition and "full-scale" is a point 1/2 lsb beyond the code transition to all ones. the deviation is measured from the middle of each particular code. units in lsbs. full-scale error - fsep the deviation of the last code transition from the ideal (vref-3/2 lsbs). units in lsbs. offset error - vos the deviation of the mid-scale transition from the ideal (1/2 lsb below 0 volts). units in lsbs. spurious-free-dynamic-range - sfdr the ratio of the rms value of the full-scale signal, to the rms value of the next largest spectral component (excepting dc). this component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. units in dbc (decibels relative to the carrier). total harmonic distortion - thd the ratio of the rms sum of the significant harmonics (2nd thru 7th), to the rms value of the full-scale signal. units in decibels. dynamic range - dr the ratio of the rms value of the inferred full-scale signal, to the rms sum of the broadband noise signals below the nyquist rate (excepting dc and distortion terms). expressed in decibels. dynamic range is tested with a 22 khz input signal 60 db below full scale. 60 db is then added to the resulting number to refer the noise level to the full-scale signal. this technique ensures that the distortion components are below the noise level and do not affect the measurement. signal-to-noise-and-distortion (s/[n+d]) - sinad the ratio of the rms value of the full-scale signal, to the rms sum of all other spectral components below the nyquist rate (excepting dc), including distortion components. expressed in decibels. group delay the time delay through the digital filter section of the part. units in seconds.
cs5181 ds250pp1 19 resolution - n the number of different output codes possible. expressed as n, where 2 n is the number of available output codes. noise - a measure of the variability of the converters output when a fixed dc input (usually ground) is applied to the input and a large number of samples are taken. rms noise is determined statistically as the standard deviation of the probability density function derived from the histogram of the adc with the differential inputs shorted together and tied to an appropriate common mode voltage. common mode rejection ratio - cmrr a measure of the devices ability to cancel out the effect of a common voltage applied to both of its differential inputs. cmrr is specified as the ratio of the differential signal gain to the gain for the common-mode signal. units in db. offset drift - changes in the offset error of the part after self calibration due to changes in ambient temperature. specified in microvolts per degree c, relative to the input signal. full scale drift - changes in the full scale error of the part after self calibration due to changes in ambient temperature. specified in parts-per-million (ppm) of the full scale range per degree c.
cs5181 20 ds250pp1 appendix a: circuit applications several amplifier circuits have been tested with the cs5181. performance at higher frequencies is gen- erally limited by the operational amplifiers used to drive the a/d converter. figure 12 illustrates a single operational amplifier circuit which can accept a single-ended ground-ref- erenced signal and condition it for the input of the cs5181. the amplifier is ac-coupled to the signal source. in this circuit the ain- input to the cs5181 is held at a constant dc value and the ain+ input is driven (it is actually overdriven to achieve high dynamic range, but this sacrifices performance with regard to distortion). the common mode volt- age for the cs5181 input should be designed to stay between 1 v and vref + 0.25 v when driven at its ain+ and ain- inputs. the single amplifier circuit in figure 12 has the disadvantages that the common mode restriction limits the input signal range and also causes errors due to variation in the common mode voltage, as opposed to applying a balanced differential signal. figures 13 and 14 illustrate the performance of the amplifier of figure 12 operating with a 3.8 v pp in- put into the ain+ input; and with 2.0 v pp input into the ain+ input respectively. 0.15 c0g 10 k w + - +15 -15 20 w + ain- vrefout cs5181 10 k w 2200 pf 20 w 2200 pf 5 k w 10 f ++ 10 f 0.1 f 1 k w ain+ 0.1 f 0.1 f u1 figure 12. single amplifier driving only ain+, with ain- held at a steady dc value figure 13. performance of amplifier of figure 12 over- driving ain+ input to the cs5181 at 3.8 v pp test signal: 30.14 khz @ -6 db s/n = 85.46 db s/d = 71.25 db s/n+d = 71.09 db 8192 samples figure 14. performance of amplifier of figure 12 with ain+ driven at 2.0 v pp
cs5181 ds250pp1 21 figure 15 illustrates a four amplifier circuit which gives the best performance by keeping everything balanced. performance is generally limited by the amplifiers. again, the output resistors are used to scale down the input signal. figures 16 and 17 il- lustrate the performance of the cs5181 with this amplifier circuit. figure 18 illustrates a differential non-linearity plot of the converter. data for the plot was taken using a repeating ramp. figure 19 is a histogram of the dnl data in figure 18. figure 20 illustrates a noise histogram of the con- verter with its inputs shorted and connected to a proper common mode voltage. + - +15 v -15 2 k w 2 k w + - 2 k w 2200 pf 100 w 2200 pf 301 w 301 w + ain+ ain- vrefout cs5181 10 k w 10 k w 10 f 2 k w + - +15 v -15 v + - 2 k w 10 k w 2 k w +15 v -15 v u1 u2 u3 u4 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f +15 v 0.1 f -15 v 0.1 f figure 15. four amplifier balanced driver. figure 16. performance of amplifier in figure 15 test signal: 20 khz @ 0 db s/n = 93.2 db s/d = 88.6 db s/n+d = 87.2 db 8192 samples
cs5181 22 ds250pp1 test signal: 60 khz @ 0 db s/n = 92.0 db s/d = 85.9 db s/n+d = 85.0 db 8192 samples figure 17. performance of amplifier in figure 15 figure 18. cs5181 differential non-linearity plot. (data taken with repeating ramp) figure 19. histogram of dnl from figure 18 figure 20. cs5181 noise histogram, 32768 samples.
cs5181 ds250pp1 23 package outline dimensions inches millimeters dim min max min max a 0.165 0.180 4.043 4.572 a1 0.090 0.120 2.205 3.048 b 0.013 0.021 0.319 0.533 d 0.485 0.495 11.883 12.573 d1 0.450 0.456 11.025 11.582 d2 0.390 0.430 9.555 10.922 e 0.485 0.495 11.883 12.573 e1 0.450 0.456 11.025 11.582 e2 0.390 0.430 9.555 10.922 e 0.040 0.060 0.980 1.524 jedec # : ms-018 28l plcc package drawing d1 d e1 e d2/e2 b e a1 a

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